The invention relates to a display panel, and in particular to a display panel compensating RC delay in signal lines.
Typically, a display panel of a conventional liquid crystal display (LCD) device comprises a plurality of scan lines and a plurality of data lines. The scan lines are interlaced with the data lines to form an active area. A plurality of pixel electrodes and a plurality of thin film diodes or thin film transistors are formed in the active area. A scan driver and a data driver respectively provide scan signals and data signals to the scan lines and the data lines through a plurality of bonding pads. The bonding pads are assembled to form bonding areas. Each bonding area is typically connected to a fanout area having a plurality of leads to connect the scan lines and data lines respectively to the scan driver and data driver.
FIG. 1 is a display panel of a conventional LCD device. A display panel 1 comprises a plurality of scan lines GL and a plurality of data lines DL. The scan lines GL are interlaced with the data lines DL in an active area 11. A plurality of bonding pads are formed in a plurality of bonding areas 12 near the periphery of the active area 11. In order to connect the scan lines GL and data lines DL to the bonding pads in the bonding areas 12, a plurality of fanout areas 13 are formed between the bonding areas 12 and the active area 11. Each fanout area 13 comprises a plurality of leads 14 connecting the scan lines GL and data lines DL to the corresponding bonding pads. Referring to FIG. 1, in each fanout area 13, the distances between the leads 14 gradually decrease from the active area 11 to the bonding area 12. Thus, in each fanout area 13, the lengths of the leads 14 gradually decrease from the outside to the inside of the fanout area 13, so that the resistance (R) and the coupled capacitance (C) gradually decrease from the outside to the inside thereof, resulting in different RC delays between the leads 14. The difference in RC delays causes degraded image qualities, such as undesirable mura defects.